MAX105ECS+T【PDF 3/21 页】IC ADC 6BIT 800MSPS DL 80TQFP

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Detailed Description

The MAX105 is a dual, +5V, 6-bit, 800Msps flash ana-

log-to-digital converter (ADC), designed for high-

speed, high-bandwidth I&Q digitizing. Each ADC

(Figure 1) employs a fully differential, wide bandwidth

input stage, 6-bit quantizers and a unique encoding

scheme to limit metastable states to typically one error

per 10

clock cycles, with no error exceeding a maxi-

mum of 1LSB. An integrated 6:12 output demultiplexer

simplifies interfacing to the part by reducing the output

data rate to one-half the sampling clock rate. The

MAX105 outputs data in LVDS two’s complement for-

mat.

When clocked at 800Msps, the MAX105 provides a typ-

ical signal-to-noise plus distortion (SINAD) of 36.4dB

with a 200MHz input tone. The analog input of the

MAX105 is designed for differential or single-ended use

with a ±400mV full-scale input range. In addition, the

MAX105 features an on-board +2.5V precision

bandgap reference, which is scaled to meet the analog

input full-scale range.

Principle of Operation

The MAX105 employs a flash or parallel architecture.

The key to this high-speed flash architecture is the use

of an innovative, high-performance comparator design.

Each quantizer and downstream logic translates the

comparator outputs into 6-bit, parallel codes in two’s

complement format and passes them on to the internal

6:12 demultiplexer. The demultiplexer enables the

ADCs to provide their output data at half the sampling

speed on primary and auxiliary ports. LVDS data is

available at speeds of up to 400MHz per output port.

Input Amplifier Circuits

As with all ADCs, if the input waveform is changing

rapidly during conversion, effective number of bits

(ENOB), signal-to-noise plus distortion (SINAD), and

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

______________________________________________________________________________________

PIN

NAME

FUNCTION

P2I+

Primary Output Data Bit 2, I-Channel

A2I-

Complementary Auxiliary Output Data Bit 2, I-Channel

A2I+

Auxiliary Output Data Bit 2, I-Channel

65, 72

OVCCI

I-Channel Outputs, Digital Supply. Supplies I-channel output drivers and DREADY circuit. Bypass to

OGND with 0.01F in parallel with 47pF for proper operation.

66, 71

OGNDI

I-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board

for proper operation.

P3I-

Complementary Primary Output Data Bit 3, I-Channel

P3I+

Primary Output Data Bit 3, I-Channel

A3I-

Complementary Auxiliary Output Data Bit 3, I-Channel

A3I+

Auxiliary Output Data Bit 3, I-Channel

P4I-

Complementary Primary Output Data Bit 4, I-Channel

P4I+

Primary Output Data Bit 4, I-Channel

A4I-

Complementary Auxiliary Output Data Bit 4, I-Channel

A4I+

Auxiliary Output Data Bit 4, I-Channel

P5I-

Complementary Primary Output Data Bit 5, I-Channel

P5I+

Primary Output Data Bit 5, I-Channel

A5I-

Complementary Auxiliary Output Data Bit 5, I-Channel

A5I+

Auxiliary Output Data Bit 5, I-Channel

Pin Description (continued)

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